1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing the field effect transistor.
2. Description of the Related Art
A wide band-gap semiconductor such as a III-V nitride compound is preferably used as a material for high-power, high-frequency, and high-temperature semiconductor devices, because the wide band-gap semiconductor has high breakdown voltage and good thermal conductivity. For example, a field effect transistor (FET) having an aluminum gallium nitride/gallium nitride (AlGaN/GaN) hetero-structure induces two-dimensional electron gas at an interface by piezoelectric effect. The two-dimensional electron gas has high electron mobility and high carrier density so that it is widely tested for a practical use. In addition, an AlGaN/GaN hetero-structure field effect transistor (HFET) has a low ON-resistance and a fast switching speed, which realizes a high temperature operation. The above characteristics are preferable for power switching application.
Generally, the AlGaN/GaN HFET is configured as a normally-on type device, in which a current flows when a bias is not applied to a gate, and the current is blocked when a negative potential is applied to the gate. For the power switching application, it is more preferable to use a normally-off type device, in which a current is blocked when a bias is not applied to the gate, and the current flows when a positive potential is applied to the gate, so that a security is assured even when a failure occurs in a device.
To realize the normally-off type device, it is necessary to employ a metal-oxide-semiconductor field-effect transistor (MOSFET) structure. FIG. 12 is a schematic side view of a conventional MOSFET 800. A buffer layer 802 and a p-type gallium nitride (p-GaN) layer 803 are grown in this order on a substrate 801 in the MOSFET 800. Two n+-GaN regions 805 and 806, as contact layers to realize an ohmic contact between source and drain regions, are grown on a portion of the p-GaN layer 803 by an ion implantation method. An n−-GaN layer 804 called a reduced surface field (RESURF) layer is grown between gate and drain regions by the ion implantation method, so that an electric field between the gate and the drain regions is reduced and a breakdown voltage of the device is improved.
An oxide film 807 made of silicon dioxide (SiO2) or the like is grown between a source electrode 809 and a drain electrode 810, and a gate electrode 808 is grown on the oxide film 807. The gate electrode 808 is generally made of poly-silicon (Si), and may be made of a metal such as nitride/gold (Ni/Au) or tungsten silicide (WSi). The source electrode 809 and the drain electrode 810 are grown on the n+-GaN regions 805 and 806, respectively. The source electrode 809 and the drain electrode 810 are made of a metal that realizes the ohmic contact to the n+-GaN region, such as titanium/aluminum (Ti/Al) or titanium/aluminum silicon/molybdenum (Ti/AlSi/Mo).
For realizing preferable channel mobility, the MOSFET needs to be configured such that a low interface state is maintained between the oxide film and the semiconductor. With a normal Si-based MOSFET, an SiO2 thermally-oxidized film made of thermally-oxidized Si is used as the oxide film, so that a preferably low interface state is realized. On the other hand, with a nitride-compound-based MOSFET, a preferable thermally-oxidized film cannot be obtained, so that the oxide film is generally formed from SiO2 by a physical and chemical vapor deposition (p-CVD) method.
For forming the n+-GaN region and the n−-GaN region, the ion implantation method is conventionally used as described above. In the ion implantation method, an annealing process is performed for restoring a crystal defect and activating an implanted impurity ion after implanting a predetermined impurity ion. When the semiconductor is made of GaN, because crystal binding is strong, the annealing process needs to be performed at a high temperature such as 1,000° C.
On the other hand, an activation ratio of the impurity ion depends on a dose amount such that the activation ratio increases as the dose amount increases. Accordingly, even when the annealing condition for completely activating the impurity ion in the n+-GaN region with the large dose amount is employed, the activation ratio of the impurity ion in the n−-GaN region does not reach 100%, resulting in an insufficient activation. When the impurity ion is not sufficiently activated in the n−-GaN region, a leakage current increases, the electron mobility in the n−-GaN region as the RESURF layer is degraded, and resistance of the n−-GaN region increases due to the inactive impurity ion. Furthermore, when the crystal defect is not sufficiently restored, the leakage current increases and the electron mobility in the n−-GaN region is degraded.
For completely activating the impurity ion in the n−-GaN region to solve the above problems, it is necessary to perform the annealing process at a high temperature such as 1,300° C. or higher. When the annealing process is performed at a temperature of 1,300° C. for a long time, pits occur on the surface of a GaN crystal, thereby degrading a quality of the GaN/SiO2 interface and channel mobility.
On the other hand, when the dose amount of the impurity ion is increased for recovering the degradation of the electron mobility in the n−-GaN region, a difference between electron densities of the n+-GaN region and the n−-GaN region becomes small, resulting in a degradation of an effect of reducing the electric field of the n−-GaN region and a failure to assure a desired breakdown voltage.